UVM Verification

UVM based Verification  Requirements Management  Verification Planning  Linting  Directed Testing  Constrained Random Testing  Functional Simulation  Coverage Analysis  DO-254 Compliant Verification  DO-254 Compliant Documentation  Requirements Management and Traceability  DO-254 Compliant FPGA & ASIC Flow  UVM based Verification  Coverage Analysis  FPGA Level In-Target Testing DO-254 Training and Consulting RISC-V Verification  System, core, and block level verification  Cache simulator  Branch predictor simulator  IP verification with 3rd party VIP  Debugging via OpenOCD, GDB, and JTAG  Supports Synopsys VCS and Siemens Questa simulators  FPGA prototyping  Linting

Design Verification Solutions 
 
Yongatek Verification Team provides several IC design verification solutions through using an extensive range of industry gold standard tools and Verification IPs (VIP). 

Functional Verification  

Yongatek’s Functional Verification platform consists of tools that enhance productivity for design entry and HDL simulation. We apply Metric Driven Verification (MDV), using the Universal Verification Methodology (UVM). 
 
Requirements Management 

With the designs getting more complex each day, the requirements grow significantly. Besides, the growing design complexity increases the necessity of well-documented problems and design definitions. This necessity gets even more highlighted with security-critical systems like DO-254 compliant designs. We provide design requirement documentation and traceability matrixes for designs to ensure that the product is built as intended.