Design and Verification Services FPGA Flow DO-254 Compliance
Verification Process
- Functional Simulations
- Timing Simulations
- Directed Tests
- System Verilog based UVM tests
- Formal Verification
Planning Process
- DO-254 Training and Consulting Services
- FPGA Design and Verification Training
- System Verilog based UVM Verification Training
- Establish project plans and standards
- Define strategy for compliance
Requirements
- Management and Traceability
- Allocate system functions to hardware
- Create derived requirements
Implementation
- Synthesis
- Place and Route
- Timing Model
- Generate bitstream file
Design Process
- High level description of design
- Identify major components
- RTL design
Validation
- Verify design on DO-254/CTS boards
- FPGA Validation
Design and Verification Services Soc/ASIC Flow for DO-254 Compliance
System Design
- Specification
- System Model Development
- Requirement Management and Traceability
Gate Level Simulations
- STA for hand-off before backend
FPGA prototyping for ASIC with big CTS boards
Physical Design
- Floor Planning
- Place and Route
- DRC
Design
- High Level Design
- Micro Architecture Documentation
- RTL Coding with VHDL or Verilog
- Functional Simulations
- Directed Tests
- System Verilog based UVM Tests
- Formal Verification
Logic Synthesis
- Constraints
- DFT (Design for Tests) Implementation
Verification and Test Supports
- STA for sign-off before tape-out
- Test Pattern Generations
Tape-out and Fabrication
Chip Validation
Cost effective Supply Chain Management
Images Gallery

