DVB-RCS and DVB-RCS2 Turbo Encoder/Decoder

DVB-RCS/RCS2 Turbo Encoder and Decoder IP Cores are based on high performance forward error correction (FEC) designs from Yongatek team compliant with ETSI EN 301 790 and ETSI EN 301 545 standards. The IP Cores use 8/16-state duo-binary Convolutional Turbo Code (CTC) with error correction performance near Shannon limit.

Key Features for DVB-RCS Turbo Encoder and Decoder IP Core:

  • Compliant with ETSI EN 301 790 standard
  • Support for block sizes 8 to 216 bytes
  • Support for QPSK and 8-PSK modulations
  • Support for code rates of 1/3, 1/2, 2/3, 4/5 and 6/7
  • Configurable iteration number from 1 to 8
  • Throughput of 101.8 Mbps at 185MHz, 8 iteration, 216 bytes

Key Features for DVB-RCS2 Turbo Encoder and Decoder IP Core:

  • Compliant with ETSI EN 301 545 standard
  • Support for block sizes 14 to 599 bytes
  • Support for π/2 BPSK, QPSK, 8-PSK and 16QAM modulations
  • Support for code rates of 1/3, 1/2, 2/3, 3/4, 4/5, 5/6, 6/7 and 7/8
  • Configurable iteration number from 1 to 8
  • Throughput of 74.8 Mbps at 175MHz, 8 iteration, 264 bytes